This invention relates to a bipolar transistor wherein a buried collector region, a base region and an emitter region are formed in a device forming region surrounded by an isolation region and wherein the emitter region is formed by the intermediary of a semiconductor layer isolated by a sidewall insulating layer. More particularly, it relates to a bipolar transistor in which a base contact electrode and a collector contact electrode are arranged in symmetry with each other.
There is proposed in the art the structure of a bipolar transistor operating at an extremely high speed wherein base contact and collector contact are achieved by having a base contact electrode and a collector contact electrode extended to a device forming region from the end of a region delimited or surrounded by an isolation region.
FIG. 6 shows in cross-section such a bipolar transistor in which the base contact electrode is arranged in symmetry with the collector contact electrode. A buried collector region 102 is formed on a semiconductor substrate 101 and a N type epitaxial layer 103 is formed on the collector region 102. An isolation region 104 is formed surrounding the layer 103. This N type epitaxial layer 103 serves as a device forming region. Within the N type epitaxial layer 103, there are formed a N.sup.+ type collector contact region 108a and a N type collector contact region 108b for electrical connection with the buried collector region, an intrinsic base region 109, a graft base region 110 and an emitter region 111. In an opening region 105 on the surface of the N type epitaxial layer 103, there are formed a base contact electrode 106 and a collector contact electrode 107 covered by an insulating layer in symmetry with each other. A thin polycrystal silicon layer 112 is formed on the insulating layer covering the contact electrodes 106 and 107.
The collector of the above described prior-art bipolar transistor is connected by way of the buried collector region 102, N.sup.+ type collector contact region 108a and the N type collector contact region 108b to the collector contact electrode 107, while the base of the transistor is connected by way of the intrinsic base region 109 and the graft base region 110 to the base contact electrode 106.
In the above described prior-art bipolar transistor, the following problems are encountered in connection with transistor characteristics.
That is, with shrinking in the dimension of the device components, the interval between the intrinsic base region 109 and the N type collector region 108b is reduced. In such case, the P type intrinsic base region 109 and the N type collector contact region 108b collide against each other, thus resulting in the reduced collector to base breakdown voltage and increased parasitic capacitance.
On the other hand, it is desired to increase the impurity concentration of the N type collector contact region 108b to lower the resistance of the region 108b. However, the collector resistance is necessarily unable to the lowered since the impurity regions again may collide against each other in case the impurity concentration is increased.